GTECH consists of basic logic gates and flops, while DW contains complex cells as adder, comparators, etc. DC translates HDL desc to components extracted from GTECH(generic tech) and DW(Design Ware) lib called as RTL opt. RTL opt: HDL-Compiler compiles HDL (performs translation and arch opt of design). This reset tree built in DC is again rebuilt in PnR during placement to make sure it meets recovery/removal checks.ġ. Reset and all other pins are buffered as needed to meet DRC. In synthesis, clk and scan_enable are set as ideal network, so they don't get buffered (they get buffered in PnR). Published: Wednesday, 26 September 2018 05:25ĭC (Design Compiler): This is the synthesis tool from Synopsys, which takes RTL as input and generates a synthesized netlist.įor running synthesis in Design Compiler: Last Updated: Thursday, 22 July 2021 22:53
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